I am a Hardware Engineer at Google. I received my Ph.D. in Computer Science from University of California Riverside under supervision of Dr. Nael Abu-Ghazaleh.
The main focus of my research has been in the area of computer architecture. More specifically, I've been working on GPU compiler & architecture solution design, efficient GPU utilization for Machine Learning purposes, and architectural support for security.
I received my M.Sc. in Computer Science from University of California Riverside, and my B.Sc. in Computer Engineering from Sharif University of Technology in Tehran, Iran. Here is my CV.
May 2021
I defended my PhD dissertation titled "Enhanced Register Data-Flow Techniques for High-Performance, Energy-Efficient GPUs". Officially a Doctor now :-)
Apr. 2021
I will be joining Google as an ASIC Design Verification Engineer (Sunnyvale, CA)!
Mar. 2021
Our paper, "BlockMaestro: Enabling Programmer-Transparent Task-based Execution in GPU Systems" has been accepted for presentation in the 48th IEEE/ACM International Symposium on Computer Architecture (ISCA), Worldwide Event.
Nov. 2020
Tech. disclosure filed for our BOW design to improve performance and energy efficiency of GPUs!
Sep. 2020
I will be doing another Google internship in Fall'20; working on ML for DV as a Hardware Engineering Intern!
July 2020
Our paper, "BOW: Breathing Operand Windows to Exploit Bypassing in GPUs" has been accepted for presentation in the 53rd IEEE/ACM International Symposium on Microarchitecture (MICRO), Athens, Greece.
May 2020
I will be joining Google as a Hardware Engineer Intern for the summer'20!
Our paper, "Locality-aware GPU Register File" has been accepted in IEEE Computer Architecture Letters (CAL).
Apr. 2019
I will be joining Google as a Hardware Engineer Intern for the summer'19, Sunnyvale, CA.
Nov. 2018
Our paper, "CORF: Coalescing Operand Register File for GPUs" has been accepted for presentation in 24th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Providence, RI, USA.
Oct. 2018
I will be the instructor for CS161 "Design and Architecture of Computer Systems" in Winter/Spring 2019. The course covers ISA, processor design, pipelining, cache hierarchy, and virtual memory.
Jul. 2018
Our paper, "In-Register Parameter Caching for Dynamic Neural Nets with Virtual Persistent Processor Specialization" has been accepted for presentation in 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Fukuoka City, Japan.
Mar. 2018
Our paper, "RegMutex: Inter-Warp GPU Register Time-Sharing" has been accepted for presentation in 45th ACM/IEEE International Symposium on Computer Architecture (ISCA), Los Angeles, CA. (Acceptance Rate = 16.9%).
Jun. 2017
I received my M.Sc. in Computer Science from University of California, Riverside.
Feb. 2017
I successfully defended my Oral Qualifying Exam. Ph.D. candidate now!
Feb. 2017
Our paper, "RIC: Relaxed Inclusion Caches for Mitigating LLC Side-Channel Attacks" has been accepted for presentation in 54th Design Automation Conference(DAC), Austin, TX.