Our paper, "Locality-aware GPU Register File" has been accepted in IEEE Computer Architecture Letters (CAL).
I will be joining Google as a Hardware Engineer Intern for the summer'19, Sunnyvale, CA.
Our paper, "CORF: Coalescing Operand Register File for GPUs" has been accepted for presentation in 24th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Providence, RI, USA.
I will be the instructor for CS161 "Design and Architecture of Computer Systems" in Winter/Spring 2019. The course covers ISA, processor design, pipelining, cache hierarchy, and virtual memory.
Our paper, "In-Register Parameter Caching for Dynamic Neural Nets with Virtual Persistent Processor Specialization" has been accepted for presentation in 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Fukuoka City, Japan.
Our paper, "RegMutex: Inter-Warp GPU Register Time-Sharing" has been accepted for presentation in 45th ACM/IEEE International Symposium on Computer Architecture (ISCA), Los Angeles, CA. (Acceptance Rate = 16.9%).
I received my M.Sc. in Computer Science from University of California, Riverside.
I successfully defended my Oral Qualifying Exam. Ph.D. candidate now!
Our paper, "RIC: Relaxed Inclusion Caches for Mitigating LLC Side-Channel Attacks" has been accepted for presentation in 54th Design Automation Conference(DAC), Austin, TX.